The exponential growth in on-chip power and current density due to CMOS scaling leads to two major challenges in the physical design of electronic devices. Including processors and memory: 1) delivering a stable voltage supply to the electronics; 2) managing heat transfer to avoid high temperature of electronic devices. When the supply voltage deviates too significantly from the nominal, timing errors can occur. When temperature becomes too high at some location of a device, the device cannot function properly and its life time is dramatically shortened.
The components of an electronic device can only function properly under a given range of voltage supply and temperature. Variation in the voltage supply beyond the allowed range is called voltage supply noise. Temperature in excess of the allowed range is called temperature violation. Voltage supply noise occurs due to the electrical resistance, electrical capacitance, and electrical inductance of the components of the power delivery network (PDN), such as the package, the controlled-collapse-chip-connection (C4) pads that connect the package to the PDN, and the PDN wires themselves. Recent studies show that transient inductive noise, proportional to instant current change (di/dt) and electrical inductance, is expected to represent a larger proportion of total noise in future process technologies (Documents 1 and 12).
Both voltage supply noise and temperature violators are sensitive to the allocations of the power pads, the transistor-cells, the decoupling capacitors (decaps), or other electrical units. In the disclosed embodiments, the effect of C4 power supply pad allocation on transient voltage noise is explored. As the interface between the package and the chip, C4 pads play a crucial role in determining the impedance of the whole power delivery system. C4 pads are used for both power delivery and I/O; while allocating additional C4 pads for power delivery can minimize voltage noise, doing so may reduce available I/O bandwidth, because C4 pads are a scare resource. Optimizing power pad count and placement, beyond improving stability or performance by reducing voltage noise, also exposes opportunities to increase I/O bandwidth, a critical bottleneck in modern SoC design.
Prior work has targeted resistive voltage noise (also called IR drop) and optimized pad location and number to minimize worst-case IR drop (Documents 13, 14, 16, 18, and 19). All these state-of-the-art pad placement techniques focus only on steady-state analysis and VDD pads. While previous work (Document 16) suggests reducing transient noise with IR-based-optimization, it is observed that such optimization has limited benefit.
Pad placement optimization for transient noise mitigation is characterized by an enormous design space combined with costly design evaluation. First, computationally complex architectural modeling is required to derive the voltage violations needed to determine optimal pad location. VoltSpot (Document 17), for instance, calculates grid node voltage at a sub-cycle granularity in order to achieve the fidelity needed for accurate, transient PDN behavior modeling. Second, the combinatorial design space of pad placement is huge for modern chips, consisting of over 1,000 candidate pad locations, of which typically 50% or more are used for power delivery. For example, the search space for the case study—a 16 nm, 16-core Intel Penryn-like multiprocessor—is larger than 10489.
To make transient noise mitigation tractable, Walking Pads (WP), a heuristic optimization framework for fast IR-drop-optimized power pad placement is extended (Document 14). WP converts the global pad placement optimization problem into a local virtual-force balance problem allowing simultaneous movement of all pads, reducing algorithm complexity significantly over the simulated annealing (SA) and mixed integer linear program (MILP) approaches in the literature (Documents 18 and 19). The computational efficiency of WP makes VDD and GND pad placement optimization for transient violation suppression feasible. To ensure WP selects a pad placement suitable across many real-world programs (benchmarks), and thus, many PDN behaviors, optimizing placement using a benchmark representative of worst-case transient power supply behavior under a continuous execution segment of a benchmark program, a “stressmark” is proposed. This is a benchmark exhibiting extreme behavior to stress the limits of a design.
According to electrical-thermal duality, the power supply and heat transfer follow the similar physical laws and mathematical formula (Document 20). The proposed method is also applicable to improve thermal control of the electronic devices.
Document List:
Document 1: International technology roadmap for semiconductors, 2011.
Document 2: C. Bienia et al. The PARSEC benchmark suite: Characterization and architectural implications. In PACT, Oct. 2008.
Document 3: N. Binkert et al. The gem5 simulator. SIGARCH Comput. Archit. News, Aug. 2011.
Document 4: J. Chung. Modeling and Hybrid Simulation of On-chip Power Delivery Network Using an Unconditionally Stable Electromagnetic Field Solver. PhD thesis, UIUC, 2007.
Document 5: G. G. Faust et al. ArchFP: rapid prototyping of pre-RTL floorplans. In VLSI-SoC, Oct. 2012.
Document 6: K. Haghdad and M Anis. Power supply pads alignment for maximum timing yield. IEEE Trans. Circuits Syst. II, Exp. Briefs2; 58(10):697-701,2011.
Document 7: ITRS. 2011. http://www.itrs.net.
Document 8: A. Joshi et al. Automated microprocessor stressmark generation. In HPCA, Feb. 2008.
Document 9: C. R. Lefurgy et al. Active management of timing guardband to save energy in POWER7. In MICRO. Dec. 2011.
Document 10: S. Li et al. McPAT: an integrated power area, and timing modeling framework for multicore and manycore architectures. In MICRO, Dec. 2009.
Document 11: A. V. Mezhiba and E. G. Friedman. Electrical characteristics of multi-layer power distribution grids. In ISCAS, May 2003.
Document 12: M. Popovich et al. Power distribution networks with on-chip decoupling capacitors. Springer, New York, 2008.
Document 13: T. Sato, H. Onodera, and M. Hashimoto. Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. In ASP-DAC, Jan. 2005.
Document 14: K. Wang et al. Walking pads: Fast power-supply pad-placement optimization. In ASP-DAC, Jan. 2014.
Document 15: R. E. Wunderlich et al. SMARTS; accelerating microarchitechure simulation via rigorous statistical sampling. In ISCA, Jun. 2003.
Document 16: T. Yu and M. Wong. A novel and efficient method for power pad placement optimization, In ISQED, Mar. 2013.
Document 17: R. Zhang et al. Architecture Implication of Pads as a Scarce Resource. In ISCA. Jun. 2014.
Document 18: M. Zhao et al. Optimal placement of power supply pads and pins. In DAC, Jun. 2004.
Document 19: Y. Zhong and M. D. F. Wong. Fast placement optimization of power supply pads. In ASP-DAC, Jan. 2007.
Document 20: K. Skadron et al. “Temperature-aware microarchitecture: Modeling and Implementation,” ACM Trans. Archit. Code Optim., vol. 1, 2004, p. 94-125.